The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a method of forming a semiconductor structure including closely spaced III-V compound semiconductor fins and germanium-containing fins.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (finFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FinFETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Advanced hybrid channel finFETs containing both III-V compound semiconductor fins and germanium-containing semiconductor fins can be beneficial for 7 nm and beyond technology. A practical problem of forming III-V nFETs and germanium-containing pFETs is how to form the III-V compound semiconductor fins and germanium-containing semiconductor fins as close as possible to meet the ground rule requirement. In conventional processing, the III-V compound semiconductor fins and germanium-containing semiconductor fins are typically defined utilizing either lithographic patterning or a sidewall image transfer process. Both of these patterning methods cannot achieve the ground rule requirements for future technology nodes. As such, an alternative method is needed to provide III-V compound semiconductor fins and germanium-containing semiconductor fins that are closely spaced so as to meet the ground rule requirements of future technology nodes.